1. Field of the Invention
The present invention relates to a data transfer device for controlling data transfer between data storage devices in a data processing system. In particular, the invention relates to a data transfer device with a configuration by which a, CPU or the like can directly access the data storage devices and which can also provide burst transfer, so that data transfer between the data storage devices is possible in one bus cycle with less hardware than used conventionally.
2. Description of the Prior Art
FIG. 1 illustrates a data processing system using a conventional data transfer device. In the drawing, the data processing system includes a data storage device 103-1 and a data storage device 103-2 for storing data to be transmitted, and a data transfer device 101 for controlling data transfer within the system. These structural elements are connected via an address bus ABUS, a data bus DBUS, and a group of control signal lines. This configuration makes it possible to access the data storage devices 103-1 and 103-2. Addresses on the address bus ABUS show addresses in the data storage devices 103-1 and 103-2. The data bus DBUS is used as a data transfer channel. In addition, the control signal group includes a clock signal CLK for transmitting a clock pulse to each structural element, a read-write signal RW indicating the direction of the data transfer, an address strobe signal AS# indicating the validity of an address output on the address bus ABUS, a data strobe signal DS# showing the validity of data output on the data bus DBUS, and an access completed signal DC# for notifying the data transfer device 101 that the transfer of data from the data storage device 103-1 or 103-2 has been completed. Further, as explained below, the # symbol following the symbol name indicates that this signal is a negative logic signal. For example, a direct memory access controller (DMAC), a microprocessor unit (MPU), or the like can function as the data transfer device 101. Also, a RAM, ROM, I/O board or the like can be used as the data storage device 103-1 or the data storage device 103-2. When a RAM is used, for example, there are cases where a large number of memory elements are provided in the interior of the RAM and the various addresses are distributed among these memory elements. The following explanation will treat the data storage devices 103-1 and 103-2 as RAMs, each provided with a large number of memory elements, but the same discussion is possible in the case where one of the data storage devices 103-1 and 103-2 has one address only, as with an I/O port. In a data processing system with this type of configuration, when transmitting data from the data storage device 103-1 to the data storage device 103-2, the data transfer device 101 first reads out data from the data storage device 103-1, then saves this data temporarily in a temporary register 112 in the data transfer device. The data transfer device 101 then writes the data which has been temporarily stored in the temporary register 112 into the data storage device 103-2. This operation is now explained in detail using a timing chart as illustrated in FIG. 2. An address in the data storage device 103-1 is stored in advance in an address register AR1 for a control section 111; an address for the data storage device 103-2 is stored in advance in an address register AR2. First, the control section 111 in the data transfer device 101 outputs to the address bus ABUS a source address for the data storage device 103-1 which is stored in the address register AR1, and outputs an `H` level signal showing a read cycle to the read-write signal RW, respectively, for a bus control section 113 to commence data transfer, and, at the same time the address strobe signal AS# is activated (time (a) on the chart). Next, at a time (b), the control section 111 issues an instruction to activate the data strobe signal DS# for the bus control section 113. When the data storage device 103-1 detects that the address strobe signal AS# has been activated, the data storage device 103-1 decodes the source address on the address bus ABUS, recognizes that this address points out a memory element in the data storage device 103-1, and outputs the pertinent data on the data bus DBUS at the time (b) when the data strobe signal DS# is activated. In addition, an access-completed signal DC# is activated in only half a clock period at a time (c), to show that the data transfer has been completed. When the control section 111 in the data transfer device 101 detects that the access-completed signal DC# has been activated, the data on the data bus DBUS is introduced into the internal temporary register 112 at a time (d), the address strobe signal AS# and the data strobe signal DS# are inactivated, and the read cycle is completed. Next, the control section 111 in the data transfer device 101 outputs to the address bus ABUS a destination address which points out a memory element in the data storage device 103-2 stored in the address register AR2, in order to write the data contained in the temporary register 112 into the data storage device 103-2 at the time (d), and outputs an `L` level signal indicating a write cycle to a read-write signal line RW, respectively, and, at the same time indicates to the bus control section 113 that the address strobe signal AS# has been activated. Further, at a time (e), the control section 111 outputs the data in the temporary register 112 to the data bus DBUS and indicates that the data strobe signal DS# has been activated. When the data storage device 103-2 recognizes from the read-write signal RW that a write cycle has been commenced, the access-completed signal DC# is activated in only half a clock period, at a time (f), and the data on the data bus DBUS is stored at a time (g). When the control section 111 in the data transfer device 101 detects that the access-completed signal DC# has been activated, the completion of the data transfer is recognized, and the write cycle is terminated at a time (g). With this type of conventional data transfer device 101, two bus cycles corresponding to a read cycle and a write cycle are required to transmit data from the data storage device 103-1 to the data storage device 103-2. At the present time, as a result of the remarkable achievements being made in increasing the speed of the central processing, there is a large difference between the operating speed of the CPU and the speed of the data storage device (for example, a DRAM). For this reason, the data transfer time makes up a relatively large proportion of the total processing time. As a result, the increase in the time necessary for transfer causes a reduction in the total processing throughput. There are also physical limits to the improvement of the speed of the external devices themselves, so the present conditions are not very desirable. Accordingly, in data transfer between the CPU and the data storage devices 103-1 and 103-2, and between the data storage device 103-1 and the data storage device 103-2, it is desirable to improve the control method for the data transfer device 101, to reduce the data transfer time. Accordingly, a direct memory access control system has been proposed wherein data is transmitted between memories, for example, between a memory and an I/O memory, within one bus cycle. An explanation of this system is given below, in summary, as a second conventional example of a conventional device, with reference to FIGS.3A, 3B, 4A, and 4B. FIG. 3A is a configuration drawing of a data processing system which uses a direct memory access controller (hereinafter referred to as a DMAC for short), as a second conventional example of a data transfer device.
FIG. 3B is a configuration drawing of the DMAC. In FIG. 3A, the data processing system comprises a main memory 201, a DMAC 202, a plurality of I/O memories 203a, 203b, and 203c, and a processing device 204, such as a microprocessor unit (MPU). The elements 201, 202, 203a, 203b, 203c, and 204 which make up the system are connected in common through a data bus 206 so that data transfer among these devices is possible. A local control signal line 207 connects the main memory 201, the MPU 204, and the DMAC 202. A system control signal line 208 and a system address bus 210 interconnect the DMAC 202, as well as the I/O memories 203a, 203b, and 203c. A local address bus 209 interconnects the main memory 201, the MPU 204, and the DMAC 202. In addition, in the data transfer system of FIG. 3B, the DMAC 202 comprises a DMAC control circuit 214, a first address register 212a, a second address register 212b, a first address renewal circuit 213a, and a second address renewal circuit 213b. The second address register 212b is connected to the local address bus 209, and the first address register 212a is connected to the system address bus 210. For this type of configuration, FIG. 4A is a timing chart for the case where data is transmitted from the main memory 201 to the I/O memory 203a. FIG. 4B is a timing chart for the case where data is transmitted from the I/O memory 203a to the main memory 201. In the case illustrated in FIG. 4A, first, the MPU 204 using the data bus 206 and the local control signal line 207 sets a destination address contained within the I/O memory 203a into a first address register, and sets a source address for the main memory 201 into a second address register 212b, respectively. Also, the data transfer direction and the number of bytes to be transmitted are set in the DMAC control circuit 214, and the DMAC 202 is started. In the DMAC 202, the DMAC control circuit 214 outputs the contents of the first address register 212a as an address signal MAD-P to the local address bus 209, and outputs the contents of the second address register 212b as an address signal AD-P to the system address bus 210. Next, a signal MMEMR-N to provide an address on the local address bus 209 to the data bus 206 is activated in the local control signal line 207.
As a result, the main memory 201 outputs data for an address shown by the second address register 212b, as a signal DT-P for the data bus 206. Data from the main memory 201 awaits output, and the DMAC control circuit 214 activates a signal MEMW-N in the system control signal line 208, which indicates the write-in of a value of the data bus 206 in the address of the I/O memory 203a shown by the system address bus 210. As a result, the operation of writing-in the data transfer destination shown by the system address bus 210 is carried out. After data is written into the I/O memory 203a, the signals MMEMR-N and MEMW-N are inactivated, and control of transfer of a data series is concluded. It is possible to control data transfer within one bus cycle. In addition, in the case of FIG. 4B, it is possible to control data transfer from the I/O memory 203a to the main memory 201 within one bus cycle in the same manner. Also, with the second conventional example of the data transfer device shown in FIGS.3A, 3B, data transfer at highest speed is possible by simultaneously outputting an address to the local address bus 209 and the system address bus 210, but there is the drawback that the total number of address buses is doubled. Accordingly, in order to eliminate this drawback, a configuration is proposed in JPTO-2-307149 which differs from the above-mentioned configuration by having an address latch between the local address bus 209 and the system address bus 210, connected to the local address bus 209, so that the outputs from the first address register 212a and the second address register 212b in the DMAC 202 are switched by a selector, or a configuration wherein an address latch is provided in the I/O memories 203a, 203b, and 203c, connected to the local address bus so that the configuration outputs an address under time-sharing to the local address bus 209 and implements data transfer control within one bus cycle. With this method, the number of address buses is small in comparison with the second conventional example shown in FIGS.3A, 3B and with modifications of the method, and there are advantages over and above the system configuration, but there is the problem that high speed output is impeded for the part of the address which is output under time sharing. In addition, the structure of the second conventional example shown in FIGS.3A, 3B and its modifications is such that data cannot be transmitted between the MPU 204 and the I/O memories 203a, 203b, and 203c, so that it is impossible to have direct access between these devices. Accordingly, in these embodiments of the data transfer device, when data is transmitted between the MPU and an I/O memory this data must be transmitted via the DMAC 202, which adds to the costs. Further, in the first conventional example shown in FIG. 1, the size of the temporary register provided in the data transfer device 101 (DMAC 202) for temporarily storing the transmitted data is limited (normally, about one word, the same width as the data bus DBUS) so that it is impossible to continuously read-out and once again write-in a greater amount of data. For this reason, there is the problem that in transfer or the like in the DRAM, continuous transfer of a plurality of data words using high speed page mode or the like (hereinafter referred to as burst transfer) cannot be performed. Furthermore, nothing is disclosed about a function for burst transfer in connection with the second conventional example and its modifications.
As stated above, with these conventional data transfer devices, there are the drawbacks that:
(1) For data transfer between a pair of data storage devices, two bus cycles--a read cycle and a write cycle--are required; PA1 (2) Even with data transfer devices with a configuration by which data transfer can be controlled within one bus cycle, the total number of address buses is doubled, or high speed output is impeded for the part of the address which is output under time sharing, and, in addition, direct access between the processing device and the data storage device is not possible; and PA1 (3) Burst transfer is not possible. PA1 a first bus control means for transferring addresses to the first data storage means through the first address bus, and for controlling input and output of a group of first control signals required to access the first data storage means; PA1 a second bus control means for transferring addresses in the second data storage means through the second address bus, and for controlling input and output of a group of second control signals required to access the second data storage means; and PA1 a control means for inputting address on the first data bus, address on the second data bus, the group of first control signals and the group of second control signals, and selecting one of them based on the control signals from the first bus control means to supply the first data storage means, and for executing data transfer in one cycle by executing simultaneous address specification to the first bus control means and the second bus control means. PA1 the first control signal group includes a high speed transfer mode signal for activating data transfer between the first data storage means and second data storage means during the data transfer in one cycle; PA1 the control means selects a first address bus value as an address corresponding to the first data storage device during activation of the high speed transfer mode signal, and when a read-out or write-in operation is specified to the second data storage device, the converse operation is specified with to the first data storage device. PA1 the first bus control means outputs a burst transfer signal which activates the continuous transfer of a plurality of data words as a package between the first data storage means and the second data storage means; PA1 the first bus control means and the second bus control means provide control during the activation of the burst transfer signal, which continues so that even after the first data transfer to the first data storage means and the second data storage means is completed, the next read-out or write-in of the address is carried out. PA1 a data transfer device provided with claim 1; PA1 data storage means for storing data comprising a first data storage means and a second data storage means; PA1 bus means for connecting among the data transfer means, the first data storage means and the second data storage means to transfer the data; and PA1 a CPU for controlling the data transfer between the first data storage means and the second data storage means, PA1 wherein the CPU accesses directly the data transfer between the first data storage means and the second data storage means under the control of the control means. PA1 a data transfer device provided with claim 1; PA1 a first data storage means for storing data; PA1 a second data storage means for storing data; PA1 bus means for connecting among the data transfer means, the first data storage means and the second data storage means; and PA1 a CPU for controlling the data transfer between the first data storage means and the second data storage means, PA1 wherein at least the data transfer device and the first data storage means are formed on the same chip.